This application claims the benefit of Korean Patent Application No. 99-52224, filed Nov. 23, 1999, the disclosure of which is hereby incorporated herein by reference.
The present invention relates generally to integrated circuit devices and, more particularly, to integrated circuit devices having a delay locked loop (DLL).
The demand for integrated circuit memory devices of increasing integration densities is generally increasing. To meet this demand, integrated circuit memory devices that can process increasing amounts of data at higher speeds, while consuming less power, may be needed. Synchronous DRAMs (SDRAMs) and Rambus DRAMs (RDRAMs) have been developed for high speed memory applications and operate in synchronization with a system clock signal. Typically, the system clock signal is received via a pin and distributed to the entire device. A clock signal that reaches a region of the device more distant from the input pin may be significantly delayed with respect to another clock signal that is closer to the input pin. This delay may make it difficult to maintain synchronism between regions within a SDRAM or a RDRAM. As a result, a delay locked loop or a phase locked loop may be used to synchronize clock signals in a device. For example, an internal clock signal may be generated to allow sampling in the middle of a valid data window to facilitate data reception, or to synchronize data to be transmitted with an edge of an external clock signal, which is sent to a memory controller to improve data transmission.
High integration of circuits within an integrated circuit memory device may increase the failure rate of components, such as transistors, which may deteriorate yield and reliability. Detecting defective chips and investigating the causes for failure at an early stage may reduce the deterioration in the yield and reliability of integrated circuit memory devices. A burn-in test is one method of detecting defective chips at an early stage. In a typical burn-in test, a high voltage, such as a prescribed maximum operating power supply voltage, is applied to a chip for a long period of time at a high temperature. In accordance with a conventional burn-in test, the stress applied to each component of a chip may be increased so that a defective chip may be more readily detected at an early stage.
A delay locked loop (DLL) is an internal circuit that typically operates at a high frequency of about 200 to 400 MHz during normal active operation. During burn-in testing, however, a clock frequency provided to a DLL by test equipment may be about 500 kHz to 1 MHz. High frequency burn-in test equipment is, therefore, preferred because low frequency burn-in test equipment may not allow the DLL circuit to operate normally. As a result, a proper evaluation of the DLL circuit may not be attained using such log frequency test equipment for burn-in test. U.S. Pat. No. 5,675,274 to Kobayashi et al. discloses a semiconductor clock signal generation circuit for testing a delay line loop (DLL) circuit when a large scale integration (LSI) circuit operates at a lower speed during burn-in testing than it does during normal operation. The approach to burn-in testing disclosed in the Kobayashi et al. patent is based on allowing the DLL circuit to perform the same operations at low speed during burn-in testing as it would under normal, high-speed operating conditions. Accordingly, there exists a need for improved integrated circuit devices and methods of operating same in which DLL circuits may be burn-in tested at higher frequencies that are closer to the circuits"" normal operating frequencies.
Embodiments of the present invention may include integrated circuit devices and methods of operating same that include a delayed locked loop (DLL) circuit that can be operated at a high frequency during a normal operation mode and during a test mode. The test mode may be, for example, for performing burn-in testing. For example, an integrated circuit device may include a DLL control circuit that generates a control signal that is responsive to a test mode signal. An oscillator circuit may generate a clock signal that is responsive to the test mode signal. This clock signal may be a high frequency clock signal, such as that used to drive a DLL circuit during a normal operation mode. A DLL circuit, which is responsive to the clock signal, may be configured to operate in either a test mode or a normal operation mode based on the control signal. Advantageously, by generating the clock signal at a high frequency, the DLL circuit may be evaluated during burn-in testing, for example, under conditions that are comparable to conditions during normal operation.
The clock signal may be connected to the DLL circuit by either a fuse or a switch. The fuse or switch may be opened upon completion of testing to isolate the DLL circuit from the test circuitry. By using a switch, additional testing of the DLL circuit may be subsequently performed by moving the switch to a closed position.
The DLL control circuit may include a control signal generation circuit, which is responsive to the test mode signal and generates an enable signal, and a control signal driving circuit, which is responsive to the enable signal and generates the control signal. The control signal generation circuit may include a fuse circuit that is responsive to a transition of a power up signal and generates a logic value at an output terminal based on a state of a fuse contained therein. A latch may be used, which is responsive to the transition of the power up signal, to latch the logic value at an output terminal thereof. Finally, an output logic circuit may generate the enable signal based on the states of the logic value and the test mode signal. Thus, a fuse in the control signal generation circuit may be used to program the DLL control circuit into a test mode or a normal operation mode.
In accordance with other embodiments of the present invention, an integrated circuit device may include a first selection circuit, which selects either an internal clock signal or a feedback signal in response to a test mode signal, and a second selection circuit, which selects either a reference clock signal or a first external clock signal in response to the test mode signal. A phase detector circuit may generate a phase comparison signal that is indicative of a phase difference between the signals selected by the first and second selection circuits. Finally, a synchronization circuit may adjust a phase of the internal clock signal based on the phase comparison signal. A third selection circuit may also be used to select either the first external clock signal or a second external clock signal. The synchronization circuit may be responsive to the selected first or second external clock signal. Thus, by implementing the feedback signal and the reference clock signals as high frequency signals, the synchronization circuit may be evaluated during testing under conditions that are comparable to conditions during normal operation.
A clock generation circuit, which is responsive to a system clock signal, may be used to generate the second external clock signal, the feedback signal, and the reference signal. The clock generation circuit may include a control clock generation circuit, which is responsive to the system clock signal and generates a control clock signal, a second external clock generation circuit, which is responsive to the control clock signal and generates the second external clock signal, and a phase control circuit, which is responsive to the control clock signal and generates the feedback signal and the reference clock signal.
Thus, the present invention may allow a DLL circuit or synchronization circuit to be stressed during burn-in testing, for example, in accordance with normal (i e., high frequency) operating conditions.